The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 10, 2009
Filed:
Oct. 02, 2007
David V. Horak, Essex Junction, VT (US);
Wesley C. Natzle, New Paltz, NY (US);
Merritt L. Funk, Austin, TX (US);
Kevin J. Lally, Austin, TX (US);
Daniel Prager, Hopewell Junction, NY (US);
David V. Horak, Essex Junction, VT (US);
Wesley C. Natzle, New Paltz, NY (US);
Merritt L. Funk, Austin, TX (US);
Kevin J. Lally, Austin, TX (US);
Daniel Prager, Hopewell Junction, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Tokyo Electron Limited, Tokyo, JP;
Abstract
A system, method and program product for correcting a deviation of a dimension of a feature from a target in a semiconductor process, are disclosed. The invention determines an origin of a deviation in a feature dimension from a target dimension regardless of whether it is based on processing or metrology. Adjustments for wafer processing variation of previous process tools can be fed forward, and adjustments for the process and/or integrated metrology tools may be fed back automatically during the processing of semiconductor wafers. The invention implements process reference wafers to determine the origin in one mode, and measurement reference wafers to determine the origin of deviations in another mode.