The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 18, 2008

Filed:

May. 27, 2005
Applicants:

Belgacem Haba, Cupertino, CA (US);

Masud Beroz, Livermore, CA (US);

Teck-gyu Kang, San Jose, CA (US);

Yoichi Kubota, Pleasanton, CA (US);

Sridhar Krishnan, Campbell, CA (US);

John B. Riley, Iii, Dallas, TX (US);

Ilyas Mohammed, Santa Clara, CA (US);

Inventors:

Belgacem Haba, Cupertino, CA (US);

Masud Beroz, Livermore, CA (US);

Teck-Gyu Kang, San Jose, CA (US);

Yoichi Kubota, Pleasanton, CA (US);

Sridhar Krishnan, Campbell, CA (US);

John B. Riley, III, Dallas, TX (US);

Ilyas Mohammed, Santa Clara, CA (US);

Assignee:

Tessera, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01L 23/48 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
Abstract

A microelectronic package includes a microelectronic element having faces, contacts and an outer perimeter, and a flexible substrate overlying and spaced from a first face of the microelectronic element, an outer region of the flexible substrate extending beyond the outer perimeter of the microelectronic element. The package includes a plurality of etched conductive posts exposed at a surface of the flexible substrate and being electrically interconnected with the microelectronic element, wherein at least one of the conductive posts is disposed in the outer region of the flexible substrate, and a compliant layer disposed between the first face of the microelectronic element and the flexible substrate, wherein the compliant layer overlies the at least one of the conductive posts that is disposed in the outer region of the flexible substrate. The package includes an encapsulating mold material in contact with the microelectronic element and the compliant layer, whereby the encapsulating mold material overlies the outer region of the flexible substrate.


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