The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 14, 2008
Filed:
Dec. 21, 2004
Tzu-chiang Sung, Jhubei, TW;
Chih Po Huang, HsinChu, TW;
Rann Shyan Yeh, Hsin-Chu, TW;
Jun Xiu Liu, Hsinchu, TW;
Chi-hsuen Chang, Hsinchu, TW;
Chung-i Chen, Hsinchu, TW;
Tzu-Chiang Sung, Jhubei, TW;
Chih Po Huang, HsinChu, TW;
Rann Shyan Yeh, Hsin-Chu, TW;
Jun Xiu Liu, Hsinchu, TW;
Chi-Hsuen Chang, Hsinchu, TW;
Chung-I Chen, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Co., Ltd, Hsin-Chu, TW;
Abstract
A semiconductor device includes multiple low voltage N-well (LVNW) areas biased at different potentials and isolated from a substrate by a common Nburied layer (NBL) and at least one high voltage N-well (HVNW) area. The LVNW areas are coupled to the common, subjacent NBL through a common Pburied layer (PBL). The method for forming the substrate usable in a semiconductor device includes forming the NBL in a designated low voltage area of a negatively biased P-type semiconductor substrate, forming the PBL in a section of the NBL area by implanting P-type impurity ions such as indium into the PBL, and growing a P-type epitaxial layer over the PBL using conditions that cause the P-type impurity ions to diffuse into the P-type epitaxial layer such that the PBL extends into the NBL. Low-voltage P-well areas are also formed in the P-type epitaxial layer and contact the PBL.