The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 14, 2008
Filed:
Mar. 30, 2007
Tze-chiang Chen, Yorktown Heights, NY (US);
Bruce B. Doris, Brewster, NY (US);
Rangarajan Jagannathan, Hopewell Junction, NY (US);
Hongwen Yan, Somers, NY (US);
Qingyun Yang, Poughkeepsie, NY (US);
Ying Zhang, Yorktown Heights, NY (US);
Tze-chiang Chen, Yorktown Heights, NY (US);
Bruce B. Doris, Brewster, NY (US);
Rangarajan Jagannathan, Hopewell Junction, NY (US);
Hongwen Yan, Somers, NY (US);
Qingyun Yang, Poughkeepsie, NY (US);
Ying Zhang, Yorktown Heights, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Multiple integration schemes for manufacturing dual gate semiconductor structures are disclosed. By employing the novel integration schemes, polysilicon gate MOSFETs and high-k dielectric metal gate MOSFETs are formed on the same semiconductor substrate despite differences in the composition of the gate stack and resulting differences in the etch rates. A thin polysilicon layer is used for one type of gate electrodes and a silicon-containing layer are used for the other type of gate electrodes in these integration schemes to balance the different etch rates and to enable etching of the two different gate stacks.