The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 09, 2008
Filed:
Dec. 28, 2006
Robin Hsieh, Hsin Chu, TW;
Tsai Chun Lin, Hsin-Chu, TW;
Albert Yao, Hsin-Chu, TW;
Pai-kang Hsu, Hsin-Chu, TW;
Tsung-yi Huang, Hsin-Chu, TW;
Ruey-hsin Liu, Hsin-Chu, TW;
Robin Hsieh, Hsin Chu, TW;
Tsai Chun Lin, Hsin-Chu, TW;
Albert Yao, Hsin-Chu, TW;
Pai-Kang Hsu, Hsin-Chu, TW;
Tsung-Yi Huang, Hsin-Chu, TW;
Ruey-Hsin Liu, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
A semiconductor structure includes a first well region of a first conductivity type overlying a substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate and laterally adjoining the first well region, a third well region of the second conductivity type adjacent and spaced apart from the first well region, a first deep well region of the second conductivity type underlying at least portions of the first and the second well regions, a second deep well region of the second conductivity type underlying the third well region and spaced apart from the first deep well region, an insulation region in the first well region, a gate dielectric extending from over the insulation region to over the second well region, and a gate electrode on the gate dielectric.