The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 05, 2008
Filed:
Nov. 08, 2005
Yi-cheng Liu, Taipei, TW;
Jiunn-ren Hwang, Hsin-Chu, TW;
Wei-tsun Shiau, Kao-Hsiung Hsien, TW;
Cheng-tung Huang, Kao-Hsiung, TW;
Kuan-yang Liao, Taipei, TW;
Yi-Cheng Liu, Taipei, TW;
Jiunn-Ren Hwang, Hsin-Chu, TW;
Wei-Tsun Shiau, Kao-Hsiung Hsien, TW;
Cheng-Tung Huang, Kao-Hsiung, TW;
Kuan-Yang Liao, Taipei, TW;
United Microelectronics Corp., Hsin-Chu, TW;
Abstract
A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate having a main surface is prepared. A gate dielectric layer is formed on the main surface. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A silicon nitride spacer is formed on the liner. The main surface is then ion implanted using the gate electrode and the silicon nitride spacer as an implantation mask, thereby forming a source/drain region of the MOS transistor device in the main surface. The silicon nitride spacer is removed. A silicon nitride cap layer that borders the liner is deposited. The silicon nitride cap layer has a specific stress status.