The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 25, 2007
Filed:
May. 06, 2004
Chao-lung Chen, Tainan, TW;
Kei-wei Chen, Taipei, TW;
Shih-ho Lin, Tainan, TW;
Ying-lang Wang, Taichung County, TW;
Yu-ku Lin, Hsin-chu, TW;
Ching-hwanq Su, Tainan, TW;
Po-jen Shih, Tainan, TW;
Shang-chin Sung, Tainan, TW;
Chao-Lung Chen, Tainan, TW;
Kei-Wei Chen, Taipei, TW;
Shih-Ho Lin, Tainan, TW;
Ying-Lang Wang, Taichung County, TW;
Yu-Ku Lin, Hsin-chu, TW;
Ching-Hwanq Su, Tainan, TW;
Po-Jen Shih, Tainan, TW;
Shang-Chin Sung, Tainan, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
A method of electroplating a metal layer on a semiconductor device includes a sequence of biasing operations that includes a first electroplating step at a first current density followed by a second immersion step at a second current density being less than the first current density, and subsequent electroplating steps of increasing current densities beginning with a third electroplating step having a third current density that is greater than the first current density. The second, low current density immersion step improves the quality of the plating process and produces a plated film that completely fills openings such as vias and trenches and avoids hollow vias and pull-back on the bottom corners of via and trench openings. The low current density second immersion step produces an electrochemical deposition process that provides low contact resistance and therefore reduces device failure.