The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 25, 2007

Filed:

Apr. 04, 2005
Applicants:

Kun-ho Kwak, Gyeonggi-do, KR;

Sung-jin Kim, Gyeonggi-do, KR;

Soon-moon Jung, Gyeonggi-do, KR;

Won-seok Cho, Gyeonggi-do, KR;

Jae-hoon Jang, Gyeonggi-do, KR;

Hoon Lim, Seoul, KR;

Jong-hyuk Kim, In-cheon, KR;

Myang-sik Han, Gyeonggi-do, KR;

Byung-jun Hwang, Gyeonggi-do, KR;

Inventors:

Kun-Ho Kwak, Gyeonggi-do, KR;

Sung-Jin Kim, Gyeonggi-do, KR;

Soon-Moon Jung, Gyeonggi-do, KR;

Won-Seok Cho, Gyeonggi-do, KR;

Jae-Hoon Jang, Gyeonggi-do, KR;

Hoon Lim, Seoul, KR;

Jong-Hyuk Kim, In-cheon, KR;

Myang-Sik Han, Gyeonggi-do, KR;

Byung-Jun Hwang, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods of fabricating semiconductor devices are provided. An interlayer insulating layer is provided on a single crystalline semiconductor substrate. A single crystalline semiconductor plug is provided that extends through the interlayer insulating layer and a molding layer pattern is provided on the semiconductor substrate and the single crystalline semiconductor plug. The molding layer pattern defines an opening therein that at least partially exposes a portion of the single crystalline semiconductor plug. A single crystalline semiconductor epitaxial pattern is provided on the exposed portion of single crystalline semiconductor plug using a selective epitaxial growth technique that uses the exposed portion of the single crystalline semiconductor plug as a seed layer. A single crystalline semiconductor region is provided in the opening. The single crystalline semiconductor region includes at least a portion of the single crystalline semiconductor epitaxial pattern.


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