The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 20, 2007
Filed:
Aug. 01, 2005
Minh Van Ngo, Fremont, CA (US);
Arvind Halliyal, Cupertino, CA (US);
Tazrien Kamal, San Jose, CA (US);
Hidehiko Shiraiwa, San Jose, CA (US);
Rinji Sugino, San Jose, CA (US);
Dawn Hopper, San Jose, CA (US);
Pei-yuan Gao, San Jose, CA (US);
Minh Van Ngo, Fremont, CA (US);
Arvind Halliyal, Cupertino, CA (US);
Tazrien Kamal, San Jose, CA (US);
Hidehiko Shiraiwa, San Jose, CA (US);
Rinji Sugino, San Jose, CA (US);
Dawn Hopper, San Jose, CA (US);
Pei-Yuan Gao, San Jose, CA (US);
Spansion LLC, Sunnyvale, CA (US);
Abstract
A manufacturing method for a dual bit flash memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric layer with the depositing performed without using ammonia at an ultra-slow deposition rate. First and second bitlines are implanted and a wordline layer is deposited. A hard mask layer is deposited over the wordline layer. A photoresist is deposited over the wordline layer and used to form a hard mask. The photoresist is removed. The wordline layer is processed using the hard mask to form a wordline and the hard mask is removed. A reduced hydrogen, high-density data retention liner to reduce charge loss, covers the wordline and the charge-trapping dielectric layer. An interlayer dielectric layer is deposited over the data retention liner.