The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 20, 2007
Filed:
Oct. 07, 2005
Jae-eon Park, Gyeonggi-do, KR;
Ja-hum Ku, Gyeonggi-do, KR;
Jun-jung Kim, Gyeonggi-do, KR;
Dae-kwon Kang, Gyeonggi-do, KR;
Young Way Teh, Singapore, SG;
Jae-Eon Park, Gyeonggi-do, KR;
Ja-Hum Ku, Gyeonggi-do, KR;
Jun-Jung Kim, Gyeonggi-do, KR;
Dae-Kwon Kang, Gyeonggi-do, KR;
Young Way Teh, Singapore, SG;
Samsung Electronics Co., Ltd., , KR;
Chartered Semiconductor Manufacturing, Ltd., Singapore, SG;
Abstract
In a semiconductor device having a dual stress liner for improving electron mobility, the dual stress liner includes a first liner portion formed on a PMOSFET and a second liner portion formed on an NMOSFET. The first liner portion has a first compressive stress, and the second liner portion has a second compressive stress smaller than the first compressive stress. The dual stress liner may be formed by forming a stress liner on a semiconductor substrate on which the PMOSFET and the NMOSFET are formed and selectively exposing a portion of the stress liner on the NMOSFET.