The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 09, 2007

Filed:

May. 24, 2006
Applicants:

Jinghong H. LI, Poughquag, NY (US);

Yaocheng Liu, Elmsford, NY (US);

Zhijiong Luo, Carmel, NY (US);

Anita Madan, Danbury, CT (US);

Nivo Rovedo, Lagrangeville, NY (US);

Inventors:

Jinghong H. Li, Poughquag, NY (US);

Yaocheng Liu, Elmsford, NY (US);

Zhijiong Luo, Carmel, NY (US);

Anita Madan, Danbury, CT (US);

Nivo Rovedo, Lagrangeville, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/94 (2006.01); H01L 31/062 (2006.01); H01L 31/113 (2006.01); H01L 31/119 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention relates to a semiconductor device including at least one n-channel field effect transistor (n-FET). Specifically, the n-FET includes first and second patterned stressor layers that both contain a carbon-substituted and tensilely stressed single crystal semiconductor. The first patterned stressor layer has a first carbon concentration and is located in source and drain (S/D) extension regions of the n-FET at a first depth. The second patterned stressor layer has a second, higher carbon concentration and is located in S/D regions of the n-FET at a second, deeper depth. Such an n-FET with the first and second patterned stressor layers of different carbon concentration and different depths provide improved stress profile for enhancing electron mobility in the channel region of the n-FET.


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