The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 04, 2007
Filed:
Nov. 15, 2004
Kuang-hsin Chen, Jung-Li, TW;
Tang-xuan Zhong, Kaohsiung, TW;
Chien-chao Huang, Hsin-Chu, TW;
Cheng-kuo Wen, HsinChu, TW;
Di-hong Lee, Austin, TX (US);
Kuang-Hsin Chen, Jung-Li, TW;
Tang-Xuan Zhong, Kaohsiung, TW;
Chien-Chao Huang, Hsin-Chu, TW;
Cheng-Kuo Wen, HsinChu, TW;
Di-Hong Lee, Austin, TX (US);
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
A semiconductor device formed on a semiconductor substrate and a method of forming the same. In one embodiment, the semiconductor device includes a gate over the semiconductor substrate and a dielectric liner on a sidewall of the gate. The semiconductor device also includes an extension spacer adjacent and extending laterally beyond the dielectric liner along the semiconductor substrate. The semiconductor device further includes a source/drain located below an upper surface of the semiconductor substrate and adjacent a channel region under the gate. The source/drain extends under the dielectric liner and the extension spacer. The semiconductor device still further includes a silicide region over a portion of the source/drain and extending laterally beyond the extension spacer along the semiconductor substrate. Thus, the extension spacer is interposed between the dielectric liner and the silicide region located over a portion of the source/drain.