The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 29, 2007
Filed:
Jan. 30, 2004
Fan Zhang, Singapore, SG;
Kho Liep Chok, Singapore, SG;
Tae Jong Lee, Singapore, SG;
Xiaomei Bu, Singapore, SG;
Meng Luo, Singapore, SG;
Chian Yuh Sin, Singapore, SG;
Yee Mei Foong, Singapore, SG;
Luona Goh, Singapore, SG;
Liang Choo Hsia, Singapore, SG;
Huey Ming Chong, Singapore, SG;
Fan Zhang, Singapore, SG;
Kho Liep Chok, Singapore, SG;
Tae Jong Lee, Singapore, SG;
Xiaomei Bu, Singapore, SG;
Meng Luo, Singapore, SG;
Chian Yuh Sin, Singapore, SG;
Yee Mei Foong, Singapore, SG;
Luona Goh, Singapore, SG;
Liang Choo Hsia, Singapore, SG;
Huey Ming Chong, Singapore, SG;
Chartered Semiconductor Manufacturing Ltd., Singapore, SG;
Abstract
A method of manufacturing an integrated circuit provides a substrate having a semiconductor device, and includes forming an intermetal dielectric layer over the substrate and the semiconductor device. A metal wire is formed above the semiconductor device and in contact therewith and a passivation layer is formed over the intermetal dielectric layer. A bond pad is formed connected to the metal wire. A protective moat, with sidewall passivation layer, is formed through the passivation layer and the intermetal dielectric layer, and is located between the metal wire and an outside edge of the integrated circuit.