The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 15, 2007
Filed:
Jul. 26, 2004
Haowen Bu, Plano, TX (US);
PR Chidambaram, Richardson, TX (US);
Rajesh Khamankar, Coppell, TX (US);
Lindsey Hall, Plano, TX (US);
Haowen Bu, Plano, TX (US);
PR Chidambaram, Richardson, TX (US);
Rajesh Khamankar, Coppell, TX (US);
Lindsey Hall, Plano, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
Methods () are presented for transistor fabrication, in which first and second sidewall spacers () are formed laterally outward from a gate structure (), after which a source/drain region () is implanted. The method () further comprises removing all or a portion of the second sidewall spacer () after implanting the source/drain region (), where the remaining sidewall spacer () is narrower following the source/drain implant to improve source/drain contact resistance and PMD gap fill, and to facilitate inducing stress in the transistor channel.