The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 17, 2007
Filed:
Jul. 22, 2005
Myeong-soon Park, Suwon-si, KR;
Hyun-soo Chung, Hwaseong-si, KR;
In-young Lee, Yongin-si, KR;
Jae-sik Chung, Hwaseong-si, KR;
Sung-min Sim, Seongnam-si, KR;
Dong-hyeon Jang, Suwon-si, KR;
Young-hee Song, Seongnam-si, KR;
Seung-kwan Ryu, Yongin-si, KR;
Myeong-Soon Park, Suwon-si, KR;
Hyun-Soo Chung, Hwaseong-si, KR;
In-Young Lee, Yongin-si, KR;
Jae-Sik Chung, Hwaseong-si, KR;
Sung-Min Sim, Seongnam-si, KR;
Dong-Hyeon Jang, Suwon-si, KR;
Young-Hee Song, Seongnam-si, KR;
Seung-Kwan Ryu, Yongin-si, KR;
Samsung Electronics Co., Ltd, Gyeonggi-do, KR;
Abstract
A wafer level chip scale package may have a gap provided between a solder bump and a bump land. The gap may be filled with a gas. A method of manufacturing a wafer level chip scale package may involve forming a redistribution line having a first opening, forming a seed metal layer having a second opening including an undercut portion, and forming the gap using the first and the second openings.