The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 27, 2007
Filed:
May. 12, 2005
Hirokazu Sayama, Tokyo, JP;
Kazunobu Ohta, Tokyo, JP;
Hidekazu Oda, Tokyo, JP;
Kouhei Sugihara, Tokyo, JP;
Hirokazu Sayama, Tokyo, JP;
Kazunobu Ohta, Tokyo, JP;
Hidekazu Oda, Tokyo, JP;
Kouhei Sugihara, Tokyo, JP;
Renesas Technology Corp., Tokyo, JP;
Abstract
A gate insulating film () and a gate electrode () of non-single crystalline silicon for forming an NMOS transistor are provided on a silicon substrate (). Using the gate electrode () as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the NMOS transistor, whereby the gate electrode () is amorphized. Subsequently, a silicon oxide film () is provided to cover the gate electrode (), at a temperature which is less than the one at which recrystallization of the gate electrode () occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode (), and high tensile stress is applied to a channel region under the gate electrode (). As a result, carrier mobility of the NMOS transistor is enhanced.