The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 30, 2007
Filed:
Sep. 24, 2004
Min-chih Hsuan, Hsinchu, TW;
Paul Chen, Hsinchu, TW;
Hermen Liu, Hsinchu, TW;
Kun-chih Wang, Hsinchu, TW;
Kai-kuang Ho, Hsinchu, TW;
Min-Chih Hsuan, Hsinchu, TW;
Paul Chen, Hsinchu, TW;
Hermen Liu, Hsinchu, TW;
Kun-Chih Wang, Hsinchu, TW;
Kai-Kuang Ho, Hsinchu, TW;
United Microelectronics Corp., Hsinchu, TW;
Abstract
The present invention relates to a method for manufacturing a wafer level chip scale package structure including the following steps. After providing a glass substrate and a wafer comprising a plurality of chips, the active surface of the wafer is connected to the top surface of the glass substrate. The wafer is connected with the glass substrate through either bumps or pads thereon. After drilling the glass substrate to form a plurality of through holes, a plating process is performed to form a plurality of via plugs in the through holes. Afterwards, a singulation step is performed and a plurality of chip scale package structures is obtained.