The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 30, 2007

Filed:

Jun. 16, 2005
Applicants:

Chan Min Yu, Singapore, SG;

Ser Bok Leng, Singapore, SG;

Low Siu Waf, Singapore, SG;

Chia Yong Poo, Singapore, SG;

Eng Meow Koon, Singapore, SG;

Inventors:

Chan Min Yu, Singapore, SG;

Ser Bok Leng, Singapore, SG;

Low Siu Waf, Singapore, SG;

Chia Yong Poo, Singapore, SG;

Eng Meow Koon, Singapore, SG;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/495 (2006.01); H01L 23/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods of forming a semiconductor assembly are described which include a leadframe with leads having offset portions exposed at an outer surface of a material package to form a grid array. An electrically conductive compound, such as solder, may be disposed or formed on the exposed lead portions to form a grid array such as a ball grid array ('BGA') or other similar array-type structure of dielectric conductive elements. The leads may have inner bond ends including a contact pad thermocompressively bonded to a bond pad of the semiconductor chip to enable electrical communication therewith and a lead section with increased flexibility to improve the thermocompressive bond. The inner bond ends may also be wirebonded to the bond pads.


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