The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 16, 2007
Filed:
Oct. 27, 2003
Birendra N. Agarwala, Hopewell Junction, NY (US);
Hormazdyar Minocher Dalal, LaGrangeville, NY (US);
Eric G. Liniger, Sandy Hook, CT (US);
Diana Llera-hurlburt, Fishkill, NY (US);
Du Binh Nguyen, Danbury, CT (US);
Richard W. Procter, Hopewell Junction, NY (US);
Hazara Singh Rathore, Stormville, NY (US);
Chunyan E. Tian, Hopewell Junction, NY (US);
Brett H. Engel, Wappingers Falls, NY (US);
Birendra N. Agarwala, Hopewell Junction, NY (US);
Hormazdyar Minocher Dalal, LaGrangeville, NY (US);
Eric G. Liniger, Sandy Hook, CT (US);
Diana Llera-Hurlburt, Fishkill, NY (US);
Du Binh Nguyen, Danbury, CT (US);
Richard W. Procter, Hopewell Junction, NY (US);
Hazara Singh Rathore, Stormville, NY (US);
Chunyan E. Tian, Hopewell Junction, NY (US);
Brett H. Engel, Wappingers Falls, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
An edge seal around the periphery of an integrated circuit device which environmentally protects the copper circuitry from cracks that may form in the low-k interlevel dielectric during dicing. The edge seal essentially constitutes a dielectric wall between the copper circuitry and the low-k interlevel dielectric near the periphery of the integrated circuit device. The dielectric wall is of a different material than the low-k interlevel dielectric.