The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 28, 2006
Filed:
Feb. 25, 2005
Oliver Genz, Dresden, DE;
Markus Kirchhoff, Ottendorf-Okrilla, DE;
Stephan Machill, Dresden, DE;
Alexander Reb, Dresden, DE;
Barbara Schmidt, Dresden, DE;
Momtchil Stavrev, Dresden, DE;
Maik Stegemann, Dresden, DE;
Stephan Wege, Dresden, DE;
Oliver Genz, Dresden, DE;
Markus Kirchhoff, Ottendorf-Okrilla, DE;
Stephan Machill, Dresden, DE;
Alexander Reb, Dresden, DE;
Barbara Schmidt, Dresden, DE;
Momtchil Stavrev, Dresden, DE;
Maik Stegemann, Dresden, DE;
Stephan Wege, Dresden, DE;
Infineon Technologies AG, München, DE;
Abstract
A method for producing a semiconductor structure including preparing a semiconductor substrate, and generating a lower first, a middle second and an upper third masking layer on a surface of the semiconductor substrate. The method further includes forming at least one first window in the upper third masking layer, structuring the middle second masking layer using the first window for transferring the first window, structuring the lower first masking layer using the first window for transferring the first window, and enlarging the first window to form a second window. The method for further includes restructuring the middle second masking layer using the second window for transferring the second window, structuring the semiconductor substrate, using the structured lower third masking layer, restructuring the lower first masking layer using the second window, and restructuring the semiconductor substrate using the restructured lower third masking layer.