The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 17, 2006

Filed:

Jan. 09, 2004
Applicants:

Sung-min Kim, Incheon-si, KR;

Dong-gun Park, Gyeonggi-do, KR;

Sung-young Lee, Gyeonggi-do, KR;

Hye-jin Cho, Gyeonggi-do, KR;

Eun-jung Yun, Seoul, KR;

Shin-ae Lee, Gyeonggi-do, KR;

Chang-woo OH, Gyeonggi-do, KR;

Jeong-dong Choe, Gyeonggi-do, KR;

Inventors:

Sung-Min Kim, Incheon-si, KR;

Dong-Gun Park, Gyeonggi-do, KR;

Sung-Young Lee, Gyeonggi-do, KR;

Hye-Jin Cho, Gyeonggi-do, KR;

Eun-Jung Yun, Seoul, KR;

Shin-Ae Lee, Gyeonggi-do, KR;

Chang-Woo Oh, Gyeonggi-do, KR;

Jeong-Dong Choe, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 21/3205 (2006.01); H01L 21/00 (2006.01); H01L 21/20 (2006.01); H01L 21/425 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods of forming a unit cell of a metal oxide semiconductor (MOS) transistor are provided. An integrated circuit substrate is formed. A MOS transistor is formed on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate. The gate is between the source region and the drain region. The first and second spaced apart buffer regions are formed beneath the source region and the drain region and between respective ones of the source region and integrated circuit substrate and the drain region and the integrated circuit substrate.


Find Patent Forward Citations

Loading…