The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 10, 2006
Filed:
Jun. 08, 2005
William E. Bernier, Endwell, NY (US);
Charles F. Carey, Endicott, NY (US);
Eberhard B. Gramatzki, Essex Junction, VT (US);
Thomas R. Homa, Binghamton, NY (US);
Eric A. Johnson, Greene, NY (US);
Pierre Langevin, Granby, CA;
Irving Memis, Vestal, NY (US);
Son K. Tran, Endwell, NY (US);
Robert F. White, Essex Junction, VT (US);
William E. Bernier, Endwell, NY (US);
Charles F. Carey, Endicott, NY (US);
Eberhard B. Gramatzki, Essex Junction, VT (US);
Thomas R. Homa, Binghamton, NY (US);
Eric A. Johnson, Greene, NY (US);
Pierre Langevin, Granby, CA;
Irving Memis, Vestal, NY (US);
Son K. Tran, Endwell, NY (US);
Robert F. White, Essex Junction, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method and structure for coupling a semiconductor substrate (e.g., a semiconductor chip) to an organic substrate (e.g., a chip carrier). The coupling interfaces a solder member (e.g., a solder ball) to both a conductive pad on the semiconductor substrate and a conductive pad on the organic substrate. Thermal strains on the solder member during thermal cycling may be reduced by having a surface area of the pad on the semiconductor substrate exceed a surface area of the pad on the organic substrate. Thermal strains on the solder member during thermal cycling may also be reduced by having a distance from a centerline of the solder member to a closest lateral edge of the semiconductor substrate exceed about 0.25 mm.