The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 03, 2006
Filed:
Jul. 21, 2004
Zhen-cheng Wu, Hsinchu, TW;
Hung Chun Tsai, Hsinchu, TW;
Da-wen Lin, Taichung, TW;
Weng Chang, Hsinchu, TW;
Shwang-ming Cheng, Hsinchu, TW;
Mong Song Liang, Hsinchu, TW;
Zhen-Cheng Wu, Hsinchu, TW;
Hung Chun Tsai, Hsinchu, TW;
Da-Wen Lin, Taichung, TW;
Weng Chang, Hsinchu, TW;
Shwang-Ming Cheng, Hsinchu, TW;
Mong Song Liang, Hsinchu, TW;
Taiwan Semiconductor Manfacturing Company, Ltd., Hsin-Chu, TW;
Abstract
In the preferred embodiment, a gate dielectric and an electrode are formed on a substrate. A pair of spacers is formed along opposite sidewalls of the gate electrode and the gate dielectric. Spacers are preferably formed of SiCO based material or SiCN based material. The source and drain are then formed. A contact etch stop (CES) layer is formed on the source/drain regions and the spacers. The CES layer is preferably formed of SiCO based material or SiCN based material. An Inter-Level Dielectric (ILD) is then formed on the CES layer.