The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 08, 2006

Filed:

Aug. 16, 2004
Applicants:

Fujio Masuoka, Sendai, JP;

Hiroshi Sakuraba, Sendai, JP;

Fumiyoshi Matsuoka, Sendai, JP;

Syounosuke Ueno, Fujiidera, JP;

Ryusuke Matsuyama, Nara, JP;

Shinji Horii, Kasaoka, JP;

Inventors:

Fujio Masuoka, Sendai, JP;

Hiroshi Sakuraba, Sendai, JP;

Fumiyoshi Matsuoka, Sendai, JP;

Syounosuke Ueno, Fujiidera, JP;

Ryusuke Matsuyama, Nara, JP;

Shinji Horii, Kasaoka, JP;

Assignees:

Sharp Kabushiki Kaisha, Osaka, JP;

Fujio Masuoka, Miyagi, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
Abstract

A nonvolatile semiconductor storage device including: a plurality of memory cell unit groups each comprising one or more NAND nonvolatile memory cell units each comprising at least one memory cell having a control gate, a first selection transistor having a first selection gate, and a second selection transistor having a second selection gate, the memory cell unit groups each further comprising a control gate line connected to the control gate, a first selection gate line connected to the first selection gate, and a second selection gate line connected to the second selection gate; a common control gate line connected commonly to the control gate lines of different ones of the memory cell unit groups; a first common selection gate line connected commonly to the first selection gate lines of different ones of the memory cell unit groups; and a second common selection gate line connected commonly to the second selection gate lines of different ones of the memory cell unit groups; wherein the memory cells in the respective memory cell unit groups are each uniquely selected on the basis of a combination of the common control gate line and the first and second common selection gate lines.


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