The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 01, 2006
Filed:
Nov. 26, 2003
Chun Hsien Lin, Hsin Chu, TW;
Ai-sen Liu, Hsinchu, TW;
Sunny Wu, Douliou, TW;
Yu-liang Lin, Hsin-chu, TW;
Henry Lo, Hsinchu, TW;
Mei-sheng Zhou, Singapore, SG;
Chun Hsien Lin, Hsin Chu, TW;
Ai-Sen Liu, Hsinchu, TW;
Sunny Wu, Douliou, TW;
Yu-Liang Lin, Hsin-chu, TW;
Henry Lo, Hsinchu, TW;
Mei-Sheng Zhou, Singapore, SG;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
A wafer based APC method for controlling an oxide (Cu, or TaN) polish step is described and combines a feed forward model that compensates for incoming wafer variations with a feed backward model which compensates for CMP variations. The method is geared toward minimizing Rs 3σ variations. A Rs target value is inputted with metrology data from previous processes that affects the width and thickness of the copper layer. A copper thickness target and polish time for the first wafer is determined. Post CMP measurement data of the first wafer is used to modify the polish rate with a disturbance factor and an updated polish time is computed for subsequent wafers. The CMP recipe for each wafer is adjusted with metrology data and post CMP measurements. The APC method is successful in controlling copper Rs variations for the 90 nm technology node and is independent of copper pattern density.