The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 25, 2006
Filed:
May. 20, 2004
Michael P. Belyansky, Bethel, CT (US);
Joyce C. Liu, Carmel, NY (US);
Hsing Jen Wann, Carmel, NY (US);
Richard Stephen Wise, New Windsor, NY (US);
Hongwen Yan, Somers, NY (US);
Michael P. Belyansky, Bethel, CT (US);
Joyce C. Liu, Carmel, NY (US);
Hsing Jen Wann, Carmel, NY (US);
Richard Stephen Wise, New Windsor, NY (US);
Hongwen Yan, Somers, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
An FET transistor has a gate disposed between a source and a drain; a gate dielectric layer disposed underneath the gate; and a spacer on a side of the gate. The gate dielectric layer is conventional oxide and the spacer has a reduced dielectric constant (k). The reduced dielectric constant (k) may be less than 3.85, or it may be less than 7.0 (˜nitride), but greater than 3.85 (˜oxide). Preferably, the spacer comprises a material which can be etched selectively to the gate dielectric layer. The spacer may be porous, and a thin layer is deposited on the porous spacer to prevent moisture absorption. The spacer may comprise a material selected from the group consisting of Black Diamond, Coral, TERA and Blok type materials. Pores may be formed in the spacer material by exposing the spacers to an oxygen plasma.