The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 30, 2006
Filed:
Dec. 03, 2004
Hidehiko Shiraiwa, San Jose, CA (US);
Jean Yee-mei Yang, Sunnyvale, CA (US);
Jaeyong Park, Sunnyvale, CA (US);
Cyrus E. Tabery, Santa Clara, CA (US);
Hidehiko Shiraiwa, San Jose, CA (US);
Jean Yee-Mei Yang, Sunnyvale, CA (US);
Jaeyong Park, Sunnyvale, CA (US);
Cyrus E. Tabery, Santa Clara, CA (US);
Spansion LLC, Sunnyvale, CA (US);
Abstract
According to one exemplary embodiment, a method of fabricating memory array includes forming a number of hard mask lines and at least one dummy hard mask line on a layer of polysilicon, where the at least one dummy hard mask line is situated in a bitline contact region of the memory array. The method further includes removing the at least one dummy hard mask line. According to this embodiment, the method further includes forming a number of wordlines, where each of the wordlines is situated under one of the hard mask lines, and where the bitline contact region causes an irregularity in spacing of the wordlines. Two of the wordlines are situated adjacent to the bitline contact region such that the spacing between the two wordlines is substantially equal to a width of the bit line contact region.