The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 28, 2006
Filed:
Dec. 09, 2003
Fujio Ito, Hanno, JP;
Hiromichi Suzuki, Tokyo, JP;
Hiroyuki Takeno, Koganei, JP;
Hiroshi Shimoji, Hamura, JP;
Fumio Murakami, Kodaira, JP;
Keiko Kurakawa, Ome, JP;
Fujio Ito, Hanno, JP;
Hiromichi Suzuki, Tokyo, JP;
Hiroyuki Takeno, Koganei, JP;
Hiroshi Shimoji, Hamura, JP;
Fumio Murakami, Kodaira, JP;
Keiko Kurakawa, Ome, JP;
Renesas Technology Corp., Tokyo, JP;
Hitachi ULSI Systems Co., Ltd., Tokyo, JP;
Renesas Eastern Japan Semiconductor, Inc., Tokyo, JP;
Abstract
It is intended to improve the production yield of QFN (Quad Flat Non-leaded package) and attain a multi-pin structure. After a resin sealing member for sealing a semiconductor chip is formed by molding, a peripheral portion of the resin sealing member and a lead frame are both cut along a cutting line which is positioned inside (on a central side of the resin sealing member) of a line (molding line) extending along an outer edge of the resin sealing member, whereby the whole surface (upper and lower surfaces and both side faces) of each of leads exposed to side faces (cut faces) of the resin sealing member is covered with resin, thus preventing the occurrence of metallic burrs on the cut faces of the leads.