The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 21, 2006
Filed:
Apr. 08, 2005
Kazuhiko Kajigaya, Iruma, JP;
Kazuyuki Miyazawa, Iruma, JP;
Manabu Tsunozaki, Ohme, JP;
Kazuyoshi Oshima, Ohme, JP;
Takashi Yamazaki, Ohme, JP;
Yuji Sakai, Machida, JP;
Jiro Sawada, Kokubunji, JP;
Yasunori Yamaguchi, Tokyo, JP;
Tetsurou Matsumoto, Higashiyamato, JP;
Shinji Udo, Akishima, JP;
Hiroshi Yoshioka, Akishima, JP;
Hirokazu Saito, Tokorozawa, JP;
Mitsuhiro Takano, Tokorozawa, JP;
Makoto Morino, Akishima, JP;
Sinichi Miyatake, Tokyo, JP;
Eiji Miyamoto, Ohme, JP;
Yasuhiro Kasama, Tokyo, JP;
Akira Endo, Hachioji, JP;
Ryoichi Hori, Tokyo, JP;
Jun Etoh, Hachioji, JP;
Masashi Horiguchi, Kawasaki, JP;
Shinichi Ikenaga, Koganei, JP;
Atsushi Kumata, Kodaira, JP;
Kazuhiko Kajigaya, Iruma, JP;
Kazuyuki Miyazawa, Iruma, JP;
Manabu Tsunozaki, Ohme, JP;
Kazuyoshi Oshima, Ohme, JP;
Takashi Yamazaki, Ohme, JP;
Yuji Sakai, Machida, JP;
Jiro Sawada, Kokubunji, JP;
Yasunori Yamaguchi, Tokyo, JP;
Tetsurou Matsumoto, Higashiyamato, JP;
Shinji Udo, Akishima, JP;
Hiroshi Yoshioka, Akishima, JP;
Hirokazu Saito, Tokorozawa, JP;
Mitsuhiro Takano, Tokorozawa, JP;
Makoto Morino, Akishima, JP;
Sinichi Miyatake, Tokyo, JP;
Eiji Miyamoto, Ohme, JP;
Yasuhiro Kasama, Tokyo, JP;
Akira Endo, Hachioji, JP;
Ryoichi Hori, Tokyo, JP;
Jun Etoh, Hachioji, JP;
Masashi Horiguchi, Kawasaki, JP;
Shinichi Ikenaga, Koganei, JP;
Atsushi Kumata, Kodaira, JP;
Hitachi, Ltd., Tokyo, JP;
Hitachi ULSI Systems Co., Ltd., Tokyo, JP;
Abstract
A semiconductor memory device formed on a semiconductor chip comprises a plurality of first memory arrays, a plurality of second memory arrays, a first voltage generator, and a plurality of first bonding pads. The semiconductor chip is divided into a first rectangle region, a second rectangle region, and a third rectangle region and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The plurality of first memory arrays are formed in the first rectangle region. The plurality of second memory arrays are formed in the second rectangle region. The voltage generator and the plurality of first bonding pads are arranged in the third rectangle region. The plurality of first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the plurality of second memory arrays.