The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 21, 2006
Filed:
Dec. 18, 2002
Susan H. Downey, Austin, TX (US);
Sheila F. Chopin, Austin, TX (US);
Peter R. Harper, Round Rock, TX (US);
Sohrab Safai, Round Rock, TX (US);
Tu-anh Tran, Austin, TX (US);
Alan H. Woosley, Austin, TX (US);
Susan H. Downey, Austin, TX (US);
Sheila F. Chopin, Austin, TX (US);
Peter R. Harper, Round Rock, TX (US);
Sohrab Safai, Round Rock, TX (US);
Tu-Anh Tran, Austin, TX (US);
Alan H. Woosley, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
An integrated circuit is packaged using a package substrate that has a bottom side with a regular array of connection points and a top side with the integrated circuit on it. The package substrate also has vias that are present to provide electrical connection between the top and bottom sides. The vias have a via capture pad that is used to directly receive a wire bond. Thus, the wires from the integrated circuit to the top side directly contact the vias at their capture pads. In such a connection there is then no need for a trace from location where the wire is bonded on the top side to the via. This saves cost. Further this makes the package substrate useful for more than one type of integrated circuit.