The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 07, 2006

Filed:

Jul. 08, 2004
Applicants:

Fujio Masuoka, Sendai, JP;

Hiroshi Sakuraba, Sendai, JP;

Fumiyoshi Matsuoka, Sendai, JP;

Syounosuke Ueno, Fujiidera, JP;

Ryusuke Matsuyama, Nara, JP;

Shinji Horii, Kasaoka, JP;

Inventors:

Fujio Masuoka, Sendai, JP;

Hiroshi Sakuraba, Sendai, JP;

Fumiyoshi Matsuoka, Sendai, JP;

Syounosuke Ueno, Fujiidera, JP;

Ryusuke Matsuyama, Nara, JP;

Shinji Horii, Kasaoka, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/12 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for driving a nonvolatile memory device including a semiconductor substrate, an island semiconductor layer on the substrate, a memory cell having a control gate and a charge storage layer surrounding a peripheral surface of the island semiconductor layer, a first selection transistor provided between the memory cell and the substrate and having a first selection gate, a source diffusion layer between the substrate and the island semiconductor layer, a drain diffusion layer provided in an opposing end of the island semiconductor layer from the source diffusion layer, and a second selection transistor provided between the memory cell and the drain diffusion layer and having a second selection gate, the method comprising the steps of: applying a negative first voltage to the drain and the first selection gate, applying a positive second voltage to the second selection gate, and applying 0V or a positive third voltage to the source; and applying a positive fourth voltage higher than the second voltage to the control gate of the memory cell for injecting electric charges into the charge storage layer.


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