The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 21, 2006
Filed:
Nov. 21, 2003
Lawrence A. Clevenger, LaGrangeville, NY (US);
Andrew P. Cowley, Wappingers Falls, NY (US);
Timothy J. Dalton, Ridgefield, CT (US);
Mark Hoinkis, Fishkill, NY (US);
Steffen K. Kaldor, Fishkill, NY (US);
Kaushik A. Kumar, Beacon, NY (US);
Stephen M. Rossnagel, Pleasantville, NY (US);
Andrew H. Simon, Fishkill, NY (US);
Douglas C. LA Tulipe, Jr., Danbury, CT (US);
Lawrence A. Clevenger, LaGrangeville, NY (US);
Andrew P. Cowley, Wappingers Falls, NY (US);
Timothy J. Dalton, Ridgefield, CT (US);
Mark Hoinkis, Fishkill, NY (US);
Steffen K. Kaldor, Fishkill, NY (US);
Kaushik A. Kumar, Beacon, NY (US);
Stephen M. Rossnagel, Pleasantville, NY (US);
Andrew H. Simon, Fishkill, NY (US);
Douglas C. La Tulipe, Jr., Danbury, CT (US);
International Business Machines Corporation, Armonk, NY (US);
Infineon Technologies, AG, Munich, DE;
Abstract
A hardmask layer in the back end of an integrated circuit is formed from TaN having a composition of less than 50% Ta and a resistivity greater than 400 μOhm-cm, so that it is substantially transparent in the visible and permits visual alignment of upper and lower alignment marks through the hardmask and intervening layer(s) of ILD. A preferred method of formation of the hardmask is by sputter deposition of Ta in an ambient containing Nand a flow rate such that (Nflow)/(N+carrier flow)>0.5.