The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 03, 2006

Filed:

Mar. 28, 2003
Applicants:

Chung-hsing Chang, Chin-Mei, TW;

Chien-hung Lin, Hsin-Chu, TW;

Burn J. Lin, Hsin-Chu, TW;

Chia-hui Lin, Hsin-Chu, TW;

Chih-cheng Chin, Junghe, TW;

Chin-hsiang Lin, Kaohsiung, TW;

Fu-jye Liang, Kaohsiung, TW;

Jeng-horng Chen, Hsin-Chu, TW;

Bang-ching Ho, Hsin-Chu, TW;

Inventors:

Chung-Hsing Chang, Chin-Mei, TW;

Chien-Hung Lin, Hsin-Chu, TW;

Burn J. Lin, Hsin-Chu, TW;

Chia-Hui Lin, Hsin-Chu, TW;

Chih-Cheng Chin, Junghe, TW;

Chin-Hsiang Lin, Kaohsiung, TW;

Fu-Jye Liang, Kaohsiung, TW;

Jeng-Horng Chen, Hsin-Chu, TW;

Bang-Ching Ho, Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G03F 9/00 (2006.01); G03F 7/20 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for transferring a pattern from a mask to a substrate (or wafer), comprises dividing a mask generation data file into a plurality of segments. The segments include a main pattern area and a stitching area. Each stitching area contains a respective common pattern. An image of an illuminated portion of the main pattern area is formed. Connection ends of the segments in a substrate area (or wafer area) are illuminated with an illumination beam. An image of the illuminated portion of the main pattern area is formed, and a halftone gray level dosage distribution is produced in the substrate area (or wafer area) corresponding to the common pattern. The common patterns of adjacent segments substantially overlap in the substrate area (or wafer area).


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