The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 25, 2005

Filed:

May. 28, 2003
Applicants:

Valery M. Dubin, Portland, OR (US);

Chin-chang Cheng, Hillsboro, OR (US);

Makarem Hussein, Beaverton, OR (US);

Phi L. Nguyen, Hillsboro, OR (US);

Ruth A. Brain, Portland, OR (US);

Inventors:

Valery M. Dubin, Portland, OR (US);

Chin-Chang Cheng, Hillsboro, OR (US);

Makarem Hussein, Beaverton, OR (US);

Phi L. Nguyen, Hillsboro, OR (US);

Ruth A. Brain, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L023/48 ;
U.S. Cl.
CPC ...
Abstract

Multiple level interconnect structures and methods for fabricating the interconnect structures are disclosed. The interconnect structures may contain an interconnect line, an electrolessly deposited metal layer formed over the interconnect line, a via formed over the metal layer, and a second interconnect line formed over the via. Often the metal layer contains a cobalt or nickel alloy and provides an etch stop layer for formation of an opening corresponding to the via. The metal layer may provide protection to the underlying interconnect line and may replace a traditional protective dielectric layer. The metal layer is conductive, rather than dielectric, and provides a shunt for passage of electrical current between the via and the interconnect line. Similar metal layers may also be used within the interconnect structures as via liner layers and via plugs.


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