The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 25, 2005

Filed:

Oct. 22, 2003
Applicants:

Chien-mao Liao, Taipei, TW;

Tzu-en Ho, Ilan, TW;

Chang-rong Wu, Taipei, TW;

Chih-how Chang, Taipei, TW;

Sheng-wei Yang, Taipei, TW;

Sheng-tsung Chen, Tainan, TW;

Chung-yuan Lee, Taoyuan, TW;

Wen-sheng Liao, Taipei, TW;

Chen-chou Huang, Taipei, TW;

Inventors:

Chien-Mao Liao, Taipei, TW;

Tzu-En Ho, Ilan, TW;

Chang-Rong Wu, Taipei, TW;

Chih-How Chang, Taipei, TW;

Sheng-Wei Yang, Taipei, TW;

Sheng-Tsung Chen, Tainan, TW;

Chung-Yuan Lee, Taoyuan, TW;

Wen-Sheng Liao, Taipei, TW;

Chen-Chou Huang, Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L021/76 ;
U.S. Cl.
CPC ...
Abstract

A method for forming a trench isolation. A semiconductor substrate with an opening is provided, on which a mask layer is formed. A first insulating layer is conformably formed on the semiconductor substrate and the trench, and the trench is filled with the first insulating layer. The first insulating layer is anisotropically etched to below the semiconductor substrate. A second insulating layer is formed on the semiconductor substrate and the trench. The second insulating layer is planarized to expose the mask layer.


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