The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 04, 2005
Filed:
Feb. 26, 2004
Kai Tzeng, Ping-Tung, TW;
Cheng-ming Wu, Tainan, TW;
Chu-wei HU, Taichung, TW;
Jung-lieh Hsu, Tainan, TW;
Kuei-yuam Hsu, Tainain, TW;
Kai Tzeng, Ping-Tung, TW;
Cheng-Ming Wu, Tainan, TW;
Chu-Wei Hu, Taichung, TW;
Jung-Lieh Hsu, Tainan, TW;
Kuei-Yuam Hsu, Tainain, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin Chu, TW;
Abstract
A method for reducing peeling of a cross-linked polymer passivation layer in a solder bump formation process including providing a multi-level semiconductor device formed on a semiconductor process wafer having an uppermost surface comprising a metal bonding pad in electrical communication with underlying device levels; forming a layer of resinous pre-cursor polymeric material over the process surface said resinous polymeric material having a glass transition temperature (Tg) upon curing; subjecting the semiconductor process wafer to a pre-curing thermal treatment temperature below Tg for a period of time; and, subjecting the semiconductor process wafer to at least one subsequent thermal treatment temperature above Tg for a period of time to form an uppermost passivation layer.