The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 16, 2005
Filed:
Mar. 20, 2001
Yoshihide Yamaguchi, Fujisawa, JP;
Hiroyuki Tenmei, Yokohama, JP;
Kosuke Inoue, Fujisawa, JP;
Noriyuki Oroku, Yokohama, JP;
Hiroshi Hozoji, Yokohama, JP;
Shigeharu Tsunoda, Fujisawa, JP;
Naoya Kanda, Fujisawa, JP;
Madoka Minagawa, Ebina, JP;
Ichiro Anjo, Koganei, JP;
Asao Nishimura, Kokubuji, JP;
Kenji Ujiie, Higashimurayama, JP;
Akira Yajima, Ebina, JP;
Yoshihide Yamaguchi, Fujisawa, JP;
Hiroyuki Tenmei, Yokohama, JP;
Kosuke Inoue, Fujisawa, JP;
Noriyuki Oroku, Yokohama, JP;
Hiroshi Hozoji, Yokohama, JP;
Shigeharu Tsunoda, Fujisawa, JP;
Naoya Kanda, Fujisawa, JP;
Madoka Minagawa, Ebina, JP;
Ichiro Anjo, Koganei, JP;
Asao Nishimura, Kokubuji, JP;
Kenji Ujiie, Higashimurayama, JP;
Akira Yajima, Ebina, JP;
Renesas Technology Corp., Tokyo, JP;
Abstract
A semiconductor device is provided which enables a flip chip connection without use of underfill. The semiconductor device includes a semiconductor element having circuit electrodes and a circuit surface coated with a protecting film. A stress relaxation layer is provided by coating a cured thermoplastic resin onto the protecting film of the circuit surface in a manner which leaves the circuit electrodes exposed and curing it and having an inclination in the edge portion thereof. A wiring layer with wirings is connected to each of the circuit electrodes and disposed so as to make an electrical connection from the circuit electrodes, via the edge portion of the stress relaxation layer, and to a desired portion on the surface of the stress relaxation layer. A protecting film is provided thereon, and an external connection terminal is also provided.