The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 12, 2005
Filed:
Jul. 11, 2003
Tsung-hua Wu, Kaohsiung Hsien, TW;
Min-lung Huang, Kaohsiung, TW;
Shih-chang Lee, Kaohsiung, TW;
Jen-kuang Fang, Pingtung Hsien, TW;
Yung-i Yeh, Kaohsiung, TW;
Tsung-Hua Wu, Kaohsiung Hsien, TW;
Min-Lung Huang, Kaohsiung, TW;
Shih-Chang Lee, Kaohsiung, TW;
Jen-Kuang Fang, Pingtung Hsien, TW;
Yung-I Yeh, Kaohsiung, TW;
Advanced Semiconductor Engineering, Inc., Kaohsing, TW;
Abstract
A method of forming a plurality of bumps over a wafer. The wafer has an active surface having a passivation layer and a plurality of contact pads thereon. The passivation layer exposes the contact pads on the active surface. An adhesion layer is formed over the active surface of the wafer and covers both the contact pads and the passivation layer. A metallic layer is formed over the adhesion layer. The adhesion layer and the metallic layer are patterned so that the adhesion layer and the metallic layer remain on top of the contact pads. A photoresist layer is formed on the active surface of the wafer. The photoresist layer has a plurality of openings that expose the metallic layer. Flux material is deposited into the openings and then a solder block is disposed into each of the openings. A reflow process is carried out so that the solder block bonds with the metallic layer. Finally, the flux material and the photoresist layer are removed.