The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 12, 2005
Filed:
Apr. 08, 2003
Sunfei Fang, LaGrangeville, NY (US);
Keith Kwong Hon Wong, Wappingers Falls, NY (US);
Paul D. Agnello, Wappingers Falls, NY (US);
Christian Lavoie, Ossining, NY (US);
Lawrence A. Clevenger, LaGrangeville, NY (US);
Chester T. Dziobkowski, Hopewell Junction, NY (US);
Richard J. Murphy, Clinton Corners, NY (US);
Patrick W. Dehaven, Poughkeepsie, NY (US);
Nivo Rovedo, LaGrangeville, NY (US);
Hsiang-jen Huang, Fishkill, NY (US);
Sunfei Fang, LaGrangeville, NY (US);
Keith Kwong Hon Wong, Wappingers Falls, NY (US);
Paul D. Agnello, Wappingers Falls, NY (US);
Christian Lavoie, Ossining, NY (US);
Lawrence A. Clevenger, LaGrangeville, NY (US);
Chester T. Dziobkowski, Hopewell Junction, NY (US);
Richard J. Murphy, Clinton Corners, NY (US);
Patrick W. DeHaven, Poughkeepsie, NY (US);
Nivo Rovedo, LaGrangeville, NY (US);
Hsiang-Jen Huang, Fishkill, NY (US);
Infineon Technologies AG, Munich, DE;
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method of forming a salicide on a semiconductor device includes depositing a first refractory metal layer over a silicon region of a substrate, depositing a near-noble metal layer over the first refractory metal layer, and depositing a second refractory metal layer over the near-noble metal layer. The semiconductor device is annealed in a first annealing process to form a silicide layer abutting the doped region of the semiconductor device. Un-reacted portions of the near-noble metal layer and the second refractory metal layer are removed. The device may be annealed in an optional second annealing process to convert the silicide layer to a low resistance phase silicide material. Junction leakage and bridging are minimized or eliminated by embodiments of the present invention, and a smoother silicided surface is achieved.