The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6908027 B1

PDF
Full Text
Expired
Date of Patent:
Jun. 21, 2005

Filed:

Mar. 31, 2003
Applicants:

Peter Tolchinsky, Beaverton, OR (US);

Mohamad Shaheen, Portland, OR (US);

Ryan Lei, Hillsboro, OR (US);

Irwin Yablok, Portland, OR (US);

Inventors:

Peter Tolchinsky, Beaverton, OR (US);

Mohamad Shaheen, Portland, OR (US);

Ryan Lei, Hillsboro, OR (US);

Irwin Yablok, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B23K031/02 ;
U.S. Cl.
CPC ...
Abstract

More complete bonding of wafers may be achieved out to the edge regions of the wafer by constrained bond strengthening of the wafers in a pressure bonding apparatus after direct wafer bonding. The pressure bonding process may be accompanied by the application of not above room temperature.


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Tolchinsky, Peter. (2005). Complete device layer transfer without edge exclusion via direct wafer bonding and constrained bond-strengthening process (U.S. Patent No. 6908027). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6908027

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