The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 26, 2005

Filed:

May. 20, 2003
Applicants:

Eric G. Webb, Salem, OR (US);

Jonathan D. Reid, Sherwood, OR (US);

John H. Sukamto, Tualatin, OR (US);

Sesha Varadarajan, Wilsonville, OR (US);

Margolita M. Pollack, Beaverton, OR (US);

Bryan L. Buckalew, Tualatin, OR (US);

Tariq Majid, Tualatin, OR (US);

Inventors:

Eric G. Webb, Salem, OR (US);

Jonathan D. Reid, Sherwood, OR (US);

John H. Sukamto, Tualatin, OR (US);

Sesha Varadarajan, Wilsonville, OR (US);

Margolita M. Pollack, Beaverton, OR (US);

Bryan L. Buckalew, Tualatin, OR (US);

Tariq Majid, Tualatin, OR (US);

Assignee:

Novellus Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
C25D005/18 ; C25D007/12 ;
U.S. Cl.
CPC ...
Abstract

A negative bias is applied to an integrated circuit wafer immersed in an electrolytic plating solution to generate a DC current. After about ten percent to sixty percent of the final layer thickness has formed in a first plating time, biasing is interrupted during short pauses during a second plating time to generate substantially zero DC current. The pauses are from about 2 milliseconds to 5 seconds long, and typically about 10 milliseconds to 500 milliseconds. Generally, about 2 pauses to 100 pauses are used, and typically about 3 pauses to 15 pauses. Generally, the DC current density during the second plating time is greater than the DC current density during the initial plating time. Typically, the integrated circuit wafer is rotated during electroplating. Preferably, the wafer is rotated at a slower rotation rate during the second plating time than during the first plating time.


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