The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 05, 2005
Filed:
May. 01, 2002
Stephan Lassig, Danville, CA (US);
S. M. Reza Sadjadi, Saratoga, CA (US);
Vinay Pohray, Fremont, CA (US);
SI Yi LI, Milpitas, CA (US);
Thomas W. Mountsier, San Jose, CA (US);
Chiu Chi, San Jose, CA (US);
Stephan Lassig, Danville, CA (US);
S. M. Reza Sadjadi, Saratoga, CA (US);
Vinay Pohray, Fremont, CA (US);
Si Yi Li, Milpitas, CA (US);
Thomas W. Mountsier, San Jose, CA (US);
Chiu Chi, San Jose, CA (US);
Lam Research Corporation, Fremont, CA (US);
Novellus Sytems, Inc., San Jose, CA (US);
Abstract
A method of forming a damascene structure above a substrate is provided. A low-k dielectric layer is formed over the substrate, wherein the low-k dielectric layer does not have a trench stop layer. A plurality of vias are etched through the low-k dielectric layer. Via plugs are formed in the plurality of vias. A plurality of trenches are etched into the low-k dielectric layer, wherein the etching with sufficiently high via plugs minimizes facet formation at the tops of vias exposed to the etch and wherein the trench etch process removes fences caused by the via plugs. The via plugs are stripped.