The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 31, 2004
Filed:
May. 23, 2002
Chung-Yu Wang, Jung-he, TW;
Chender Huang, Hsin-Chu, TW;
Pei-Haw Tsao, Taichung, TW;
Ken Chen, Hsinchu, TW;
Hank Huang, Jungli, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin Chu, TW;
Abstract
A method for protecting a passivation layer during a solder bump formation process including providing a semiconductor process wafer having a process surface including at least two metal layers comprising an uppermost metal layer and a lowermost metal layer said lowermost metal layer overlying a passivation layer including metal bonding pad regions; photolithographically patterning and anisotropically etching through a first thickness portion of at least the uppermost metal layer to form a first patterned metal layer portion disposed over the metal bonding pad regions and reveal a second thickness portion including the lowermost metal layer; forming a solder bump over the first patterned metal layer portion according to at least a first reflow process; and, anisotropically etching through the second thickness portion surrounding the completely formed solder bump to reveal the passivation layer.