The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 24, 2004

Filed:

Apr. 18, 2003
Applicant:
Inventors:

Huajie Chen, Wappingers Falls, NY (US);

Seshadri Subbanna, Brewster, NY (US);

Basanth Jagannathan, Beacon, NY (US);

Gregory G. Freeman, Hopewell Junction, NY (US);

David C. Ahlgren, Wappingers Falls, NY (US);

David Angell, Poughkeepsie, NY (US);

Kathryn T. Schonenberg, Wappingers Falls, NY (US);

Kenneth J. Stein, Sandy Hook, CT (US);

Fen F. Jamin, Wappingers Falls, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/18238 ;
U.S. Cl.
CPC ...
H01L 2/18238 ;
Abstract

A method of forming a BiCMOS integrated circuit having a raised extrinsic base is provided. The method includes first forming a polysilicon layer atop a surface of a gate dielectric which is located atop a substrate having device areas for forming at least one bipolar transistor and device areas for forming at least one complementary metal oxide semiconductor (CMOS) transistor. The polysilicon layer is then patterned to provide a sacrificial polysilicon layer over the device areas for forming the at least one bipolar transistor and its surrounding areas, while simultaneously providing at least one gate conductor in the device areas for forming at least one CMOS transistor. At least one pair of spacers are then formed about each of the at least one gate conductor and then a portion of the sacrificial polysilicon layer over the bipolar device areas are selectively removed to provide at least one opening in the bipolar device area. At least one bipolar transistor having a raised extrinsic base is then formed in the at least one opening.


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