The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 16, 2003

Filed:

May. 15, 2001
Applicant:
Inventors:

Tee Onn Chong, Penang, MY;

Seng Hooi Ong, Penang, MY;

Robert L. Sankman, Phoenix, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 7/06 ;
U.S. Cl.
CPC ...
H05K 7/06 ;
Abstract

An electronics package comprises an integrated circuit (IC) coupled to an IC substrate in a flip-chip ball grid array (FCBGA) configuration. The IC comprises a high density pattern of interconnect pads around its periphery for coupling to a corresponding pattern of bonding pads on the IC substrate. The substrate bonding pads are uniquely arranged to accommodate a high density of interconnect pads on the IC while taking into account various geometrical constraints on the substrate, such as bonding pad size, trace width, and trace spacing. In one embodiment, the substrate bonding pads are arranged in a zigzag pattern. In a further embodiment, the technique is used for bonding pads on a printed circuit board to which an IC package is coupled. Methods of fabrication, as well as application of the package to an electronic package, an electronic system, and a data processing system, are also described.


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