The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 05, 2003
Filed:
Aug. 16, 2001
Yen-Ming Chen, Hsin Chu, TW;
Chia-Fu Lin, Hsin-Chu, TW;
Kai-Ming Ching, Taiping, TW;
Hsin-Hui Lee, Koashiung, TW;
Chao-Yuan Su, Koashiung, TW;
Li-Chi Chen, Taipei, TW;
Taiwan Semiconductor Manufacturing Company, Hsin-Chu, TW;
Abstract
A method of fabricating a solder bump including the following steps. A UBM over a substrate.having an exposed pad portion is provided. The UBM being in electrical contact with the pad portion. A first patterning layer is formed over the UBM. The first patterning layer including a photosensitive material sensitive to light having a first wavelength. A second patterning layer is formed over the first patterning layer. The second patterning layer including a photosensitive material sensitive to light having a second wavelength. The first patterning layer is selectively exposed with the light having the first wavelength, leaving a first unexposed portion substantially centered over the pad portion between first exposed portions. The second patterning layer is selectively exposed with the light having the second wavelength, leaving a second unexposed portion wider than, and substantially centered over, the first unexposed portion of the exposed first patterning layer. The second unexposed portion of the exposed second patterning layer being between exposed portions. The second unexposed portion of the exposed second patterning layer and the first unexposed portion of the exposed first patterning layer are removed to form opening. A solder plug is formed within the opening. The exposed portions of the exposed first patterning layer and the exposed portions of the exposed second patterning layer are removed. The solder plug is reflowed to form a solder bump.