The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 10, 2003

Filed:

May. 31, 2002
Applicant:
Inventors:

David A. Beauchaine, Vancouver, WA (US);

Timothy L. Brown, Vancouver, WA (US);

Sergei V. Koveshnikov, Vancouver, WA (US);

Romony San, Vancouver, WA (US);

Assignee:

SEH America, Inc., Vancouver, WA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/1335 ;
U.S. Cl.
CPC ...
H01L 2/1335 ;
Abstract

A semiconductor wafer manufacturing process is disclosed wherein a double side polished wafer having oxygen induced stacking faults to provide extrinsic gettering on the back surface of the wafer. The process includes polishing the back surface of the wafer, and depositing a thin polysilicon film on the polished back surface. The wafer is then subjected to a thermal oxidation step, wherein the polysilicon film is consumed by the thermal oxidation step. The oxide layer is then stripped from the back surface, leaving oxygen induced stacking faults on the back surface of the wafer. The front surface of the wafer is then polished, thereby producing a double side polished wafer containing extrinsic gettering sites on the polished back surface.


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