The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 25, 2003

Filed:

Dec. 18, 2000
Applicant:
Inventors:

Hidenori Akiyama, Miyagi, JP;

Paul Chang, Saratoga, CA (US);

Geeng-Chuan Chern, Cupertino, CA (US);

Wayne Y. W. Hsueh, San Jose, CA (US);

Haru Ohkawa, Miyagi, JP;

Yasuo Ohtsuki, Miyagi, JP;

Vladimir Rodov, Redondo Beach, CA (US);

Assignee:

Other;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/1332 ; H01L 2/18238 ; H01L 2/1336 ; H01L 2/1425 ;
U.S. Cl.
CPC ...
H01L 2/1332 ; H01L 2/18238 ; H01L 2/1336 ; H01L 2/1425 ;
Abstract

A method for manufacturing a discrete power rectifier device having a VLSI multi-cell design employs a two spacer approach to defining a P/N junction profile having good breakdown voltage characteristics. The method provides highly repeatable device characteristics at reduced cost. The active channel regions of the device are also defined using the same two spacers. The method is a self-aligned process and channel dimensions and doping characteristics may be precisely controlled despite inevitable process variations in spacer formation. Only two masking steps are required, and additional spacers for defining the body region profile can be avoided, reducing processing costs.


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