The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 2003

Filed:

Jun. 30, 2000
Applicant:
Inventors:

Bomy A. Chen, Ridgefield, CT (US);

Jay G. Harrington, Monroe, CT (US);

Kevin M. Houlihan, South Boston, MA (US);

Dennis Hoyniak, Essex Junction, VT (US);

Chung Hon Lam, Williston, VT (US);

Hyun Koo Lee, LaGrangeville, NY (US);

Rebecca D. Mih, Wappingers Falls, NY (US);

Jed H. Rankin, Burlington, VT (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/976 ;
U.S. Cl.
CPC ...
H01L 2/976 ;
Abstract

A method and structure for a EEPROM memory device integrated with high performance logic or NVRAM. The EEPROM device includes a floating gate and program gate self-aligned with one another. During programming, electron tunneling occurs between the floating gate and the program gate.


Find Patent Forward Citations

Chen, Bomy. (2003). Method to create eeprom memory structures integrated with high performance logic and nvram, and operating conditions for the same (U.S. Patent No. 6504207). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6504207

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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