The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 20, 2002
Filed:
Oct. 05, 2000
Cyril Cabral, Jr., Ossining, NY (US);
Chung-Ping Eng, Hopewell Junction, NY (US);
Lynne Marie Gignac, Beacon, NY (US);
Christian Lavoie, Ossining, NY (US);
Patricia O'Neil, Wappingers Falls, NY (US);
Kirk David Peterson, Essex Junction, VT (US);
Tina Wagner, Newburgh, NY (US);
Yun-Yu Wang, Poughquag, NY (US);
Keith Wong, Wappingers Falls, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure without the formation of a thick amorphous layer containing Ti, Co and Si and the structure formed are provided. In the method, after a Ti layer is deposited on top of a metal silidide layer, a dual-step annealing process is conducted in which a low temperature annealing in a forming gas (or ammonia) at a temperature not higher than 500° C. is first conducted for less than 2 hours followed by a high temperature annealing in a nitrogen-containing gas (or ammonia) at a second temperature not lower than 500° for less than 2 hours to form the TiN layer. The present invention method prevents the problem usually caused by a thick amorphous material layer of Ti—Si—Co which produces weakly bonded Ti which reacts with fluorine atoms from WF during a subsequent CVD W deposition process and causes liner failure due to a volume expansion of the amorphous material. The maximum thickness of the amorphous material layer formed by the present invention method is less than 5 nm which minimizes the line failure problem.